1. Field of the Invention
This invention relates to packaging for integrated circuit chips and, more particularly, to packaging techniques which provide improved electrical connections to an integrated circuit chip package.
2. Prior Art
Traditional package assemblies for high-performance integrated circuit packages are made of high quality ceramic materials. These packages are sealed with a lid which is electrically isolated from other electrical conductors associated with the package assembly. Often, these lids are formed of a metal or other material which is covered with a conductive material, for example, Kovar plated with gold.
It has been found that, at high frequencies, an electrically isolated, conductive lid may have some operational disadvantages. In terms of electromagnetic interference, the electrically isolated lid of the package functions as a conductive body which may, in effect, function as an antenna radiating electromagnetic interference (EMI) into the integrated circuit assembly when the integrated circuit is operated at high frequencies.
It has also been found that the self-inductance of the bonding wires and the mutual inductance between bonding wires are significant and can limit the electrical performance of an integrated circuit, particularly at high frequencies. In high performance ceramic pin-grid-array (HPCPGA) packages, the inductance of the bonding wires is a large portion of the overall inductance of a package. Since the bonding wires float with no ground plane nearby, the inductance of the bonding wires is relatively high.
With the advances in integrated circuit design and fabrication techniques, integrated circuits are operating at ever higher frequencies so that a need exists for reducing lead inductances and electromagnetic interference.